[DS60-120]am335x-evm.dts 20 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. #define PIN_OUTPUT (PULL_DISABLE)
  8. #define PIN_OUTPUT_PULLUP (PULL_UP)
  9. #define PIN_OUTPUT_PULLDOWN 0
  10. #define PIN_INPUT (INPUT_EN | PULL_DISABLE)
  11. #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
  12. #define PIN_INPUT_PULLDOWN (INPUT_EN)
  13. */
  14. /dts-v1/;
  15. #include "am33xx.dtsi"
  16. #include <dt-bindings/interrupt-controller/irq.h>
  17. / {
  18. model = "TI AM335x EVM";
  19. compatible = "ti,am335x-evm", "ti,am33xx";
  20. cpus {
  21. cpu@0 {
  22. cpu0-supply = <&vdd1_reg>;
  23. };
  24. };
  25. memory {
  26. device_type = "memory";
  27. /*reg = <0x80000000 0x10000000>;*/ /* 256 MB */
  28. reg = <0x80000000 0x20000000>; /* 512 MB */ /* +++ vern,512MB DDR ,20181030 ---*/
  29. };
  30. /* +++ vern,ramdisk,20181030 +++*/
  31. chosen {
  32. bootargs = "console=ttyS0,115200n8 root=/dev/ram0";
  33. };
  34. /* --- vern,ramdisk ,20181030 ---*/
  35. vbat: fixedregulator@0 {
  36. compatible = "regulator-fixed";
  37. regulator-name = "vbat";
  38. regulator-min-microvolt = <5000000>;
  39. regulator-max-microvolt = <5000000>;
  40. regulator-boot-on;
  41. };
  42. lis3_reg: fixedregulator@1 {
  43. compatible = "regulator-fixed";
  44. regulator-name = "lis3_reg";
  45. regulator-boot-on;
  46. };
  47. };
  48. /******************** Pin Mux ********************/
  49. &am33xx_pinmux {
  50. pinctrl-names = "default";
  51. pinctrl-0 = <&InitialGPIO>;
  52. pinctrl-1 = <&clkout2_pin>;
  53. InitialGPIO: InitialGPIO {
  54. pinctrl-single,pins = <
  55. /** Offset: 0x800 */
  56. /** GPIO 0 */
  57. 0x020 (PIN_INPUT | MUX_MODE7) /* GPMC_AD8 => GPIO0_22 */ /*ID BD1_1*/
  58. 0x024 (PIN_INPUT | MUX_MODE7) /* GPMC_AD9 => GPIO0_23 */ /*ID BD1_2*/
  59. 0x028 (PIN_INPUT | MUX_MODE7) /* GPMC_AD10 => GPIO0_26 */ /*IO BD1_1*/
  60. 0x02C (PIN_INPUT | MUX_MODE7) /* GPMC_AD11 => GPIO0_27 */ /*IO BD1_2*/
  61. 0x144 (PIN_INPUT | MUX_MODE7) /* RMII1_REF_CLK => GPIO0_29 */ /*USB 0 OCP detection*/
  62. 0x1B0 (PIN_OUTPUT | MUX_MODE7) /*XDMA_EVENT_INTR0 => GPIO0_19 */ /*AM_RFID_RST*/
  63. 0x1B4 (PIN_INPUT | MUX_MODE7) /*XDMA_EVENT_INTR1 => GPIO0_20 */ /*AM_RFID_ICC*/
  64. /** GPIO 1 */
  65. 0x030 (PIN_INPUT | MUX_MODE7) /* GPMC_AD12 => GPIO1_12 */ /*ID BD2_1*/
  66. 0x034 (PIN_INPUT | MUX_MODE7) /* GPMC_AD13 => GPIO1_13 */ /*ID BD2_2*/
  67. 0x038 (PIN_INPUT | MUX_MODE7) /* GPMC_AD14 => GPIO1_14 */ /*IO BD2_1*/
  68. 0x03C (PIN_INPUT | MUX_MODE7) /* GPMC_AD15 => GPIO1_15 */ /*IO BD2_2*/
  69. /** GPIO 2 */
  70. 0x0EC (PIN_OUTPUT | MUX_MODE7) /*LCD_AC_BIAS_EN => GPIO2_25*/ /*RS-485 for module DE control*/
  71. 0x0E4 (PIN_OUTPUT | MUX_MODE7) /*LCD_HSYNC => GPIO2_23*/ /*RS-485 for module RE control*/
  72. 0x0E8 (PIN_INPUT | MUX_MODE7) /*LCD_PCLK => GPIO2_24*/ /*CCS communication board 1 proximity*/
  73. 0x0E0 (PIN_INPUT | MUX_MODE7) /*LCD_VSYNC => GPIO2_22*/ /*CCS communication board 2 proximity*/
  74. /** GPIO 3 */
  75. 0x194 (PIN_INPUT | MUX_MODE7) /*MCASP0_FSX => GPIO3_15*/ /*Emergency Stop button detect*/
  76. 0x1A0 (PIN_INPUT | MUX_MODE7) /*MCASP0_ACLKR => GPIO3_18*/ /*USB1 OCP detect*/
  77. 0x19C (PIN_INPUT | MUX_MODE7) /*MCASP0_AHCLKR => GPIO3_17*/ /*Emergency IO for AM3352 and STM32F407*/
  78. 0x190 (PIN_OUTPUT | MUX_MODE7) /*MCASP0_ACLKX => GPIO3_14*/ /*Ethernet PHY reset*/
  79. 0x1A4 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_FSR => GPIO3_19 */ /*SMR Enable control_1*/
  80. 0x198 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR0 => GPIO3_16 */ /*CSU board function OK indicator.*/
  81. 0x1A8 (PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR1 => GPIO3_20 */ /*SMR Enable control_2*/
  82. >;
  83. };
  84. i2c0_pins: pinmux_i2c0_pins {
  85. pinctrl-single,pins = <
  86. 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  87. 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  88. >;
  89. };
  90. #if 1
  91. i2c1_pins: pinmux_i2c1_pins {
  92. pinctrl-single,pins = <
  93. 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
  94. 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  95. >;
  96. };
  97. #endif
  98. uart0_pins: pinmux_uart0_pins {
  99. pinctrl-single,pins = <
  100. 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd => uart0_rxd */
  101. 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd => uart0_txd */
  102. >;
  103. };
  104. uart1_pins: pinmux_uart1_pins {
  105. pinctrl-single,pins = <
  106. 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd => uart1_txd */
  107. 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd => uart1_rxd */
  108. >;
  109. };
  110. uart2_pins: pinmux_uart2_pins {
  111. pinctrl-single,pins = <
  112. 0x150 (PIN_INPUT_PULLUP | MUX_MODE1) /* SPI0_SCLK => UART2_RXD */
  113. 0x154 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* SPI0_D0 => UART2_TXD */
  114. >;
  115. };
  116. uart3_pins: pinmux_uart3_pins {
  117. pinctrl-single,pins = <
  118. 0x160 (PIN_INPUT_PULLUP | MUX_MODE1) /* SPI0_CS1 => uart3_rxd */
  119. 0x164 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ECAP0_IN_PWM0_OUT => uart3_txd */
  120. >;
  121. };
  122. uart5_pins: pinmux_uart5_pins {
  123. pinctrl-single,pins = <
  124. 0x0C0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* LCD_DATA8 => DUART5_TX*/
  125. 0x0C4 (PIN_INPUT_PULLUP | MUX_MODE4) /* LCD_DATA9 => UART5_RX*/
  126. >;
  127. };
  128. clkout2_pin: pinmux_clkout2_pin {
  129. pinctrl-single,pins = <
  130. 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
  131. >;
  132. };
  133. nandflash_pins_default: nandflash_pins_default {
  134. pinctrl-single,pins = <
  135. 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  136. 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  137. 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  138. 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  139. 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  140. 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  141. 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  142. 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  143. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  144. 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
  145. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  146. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  147. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  148. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  149. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  150. >;
  151. };
  152. nandflash_pins_sleep: nandflash_pins_sleep {
  153. pinctrl-single,pins = <
  154. 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  155. 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  156. 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  157. 0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
  158. 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  159. 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  160. 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  161. 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  162. 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  163. 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  164. 0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  165. 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  166. 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  167. 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  168. 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  169. >;
  170. };
  171. cpsw_default: cpsw_default {
  172. pinctrl-single,pins = <
  173. /* Slave 1 */
  174. 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* MII1_COL.gmii1_col */
  175. 0x10C(PIN_INPUT_PULLUP | MUX_MODE0) /* MII1_CRS.MII1_CRS */
  176. 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* MII1_RX_ER.gmii1_rxerr */
  177. 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
  178. 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
  179. 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
  180. 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.rgmii1_rd3 */
  181. 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.rgmii1_rd2 */
  182. 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.rgmii1_rd1 */
  183. 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.rgmii1_rd0 */
  184. 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
  185. 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.rgmii1_td3 */
  186. 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.rgmii1_td2 */
  187. 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.rgmii1_td1 */
  188. 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.rgmii1_td0 */
  189. /* Slave 2 */
  190. AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ben1.mii2_col */
  191. AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) /* GPMC_CSn3.rmii2_crs_dv*/
  192. /*AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE1)*/ /* gpmc_wpn.mii2_rxerr */
  193. AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a6.mii2_txclk */
  194. AM33XX_IOPAD(0x85c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
  195. AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
  196. AM33XX_IOPAD(0x860, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
  197. AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
  198. AM33XX_IOPAD(0x868, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
  199. AM33XX_IOPAD(0x86c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
  200. AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a0.mii2_txen */
  201. AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
  202. AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
  203. AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
  204. AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
  205. >;
  206. };
  207. cpsw_sleep: cpsw_sleep {
  208. pinctrl-single,pins = <
  209. /* Slave 1 reset value */
  210. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  211. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  212. 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  213. 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  214. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  215. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  216. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  217. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  218. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  219. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  220. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  221. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  222. /* Slave 2 */
  223. AM33XX_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* GPMC_CSn3.rmii2_crs_dv*/
  224. AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.mii2_txen */
  225. AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mii2_rxdv */
  226. AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mii2_txd3 */
  227. AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mii2_txd2 */
  228. AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.mii2_txd1 */
  229. AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.mii2_txd0 */
  230. AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.mii2_txclk */
  231. AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.mii2_rxclk */
  232. AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.mii2_rxd3 */
  233. AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.mii2_rxd2 */
  234. AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.mii2_rxd1 */
  235. AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.mii2_rxd0 */
  236. /*AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7)*/ /* gpmc_wpn.mii2_rxerr */
  237. AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben1.mii2_col */
  238. >;
  239. };
  240. davinci_mdio_default: davinci_mdio_default {
  241. pinctrl-single,pins = <
  242. /* MDIO */
  243. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  244. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  245. >;
  246. };
  247. davinci_mdio_sleep: davinci_mdio_sleep {
  248. pinctrl-single,pins = <
  249. /* MDIO reset value */
  250. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  251. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  252. >;
  253. };
  254. mmc1_pins_default: pinmux_mmc1_pins {
  255. pinctrl-single,pins = <
  256. 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
  257. 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
  258. 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
  259. 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
  260. 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
  261. 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
  262. 0x1AC (PIN_INPUT_PULLUP | MUX_MODE7) /* MCASP0_AHCLKX.GPIO3_21 */
  263. >;
  264. };
  265. dcan0_pins_default: dcan0_pins_default {
  266. pinctrl-single,pins = <
  267. 0x178 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart1_ctsn => d_can0_tx */
  268. 0x17C (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn => d_can0_rx */
  269. >;
  270. };
  271. dcan1_pins_default: dcan1_pins_default {
  272. pinctrl-single,pins = <
  273. 0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* UART0_CTSn => d_can1_tx */
  274. 0x16C (PIN_INPUT_PULLDOWN | MUX_MODE2) /* UART0_RTSn => d_can1_rx */
  275. >;
  276. };
  277. #if 0
  278. ehrpwm1_pins: ehrpwm1_pins {
  279. pinctrl-single,pins = <
  280. 0x0C8 (PIN_OUTPUT | MUX_MODE2) /* LCD_DATA10.eHRPWM1A */
  281. >;
  282. };
  283. ehrpwm2_pins: ehrpwm2_pins {
  284. pinctrl-single,pins =<
  285. 0x0A4 (PIN_OUTPUT | MUX_MODE3) /* LCD_DATA1.eHRPWM2B */
  286. >;
  287. };
  288. #endif
  289. };
  290. /******************** Peripheral Init ********************/
  291. &uart0 {
  292. pinctrl-names = "default";
  293. pinctrl-0 = <&uart0_pins>;
  294. status = "okay";
  295. };
  296. &uart1 {
  297. pinctrl-names = "default";
  298. pinctrl-0 = <&uart1_pins>;
  299. status = "okay";
  300. };
  301. &uart2 {
  302. pinctrl-names = "default";
  303. pinctrl-0 = <&uart2_pins>;
  304. status = "okay";
  305. };
  306. &uart3 {
  307. pinctrl-names = "default";
  308. pinctrl-0 = <&uart3_pins>;
  309. status = "okay";
  310. };
  311. &uart5 {
  312. pinctrl-names = "default";
  313. pinctrl-0 = <&uart5_pins>;
  314. status = "okay";
  315. };
  316. &i2c0 {
  317. pinctrl-names = "default";
  318. pinctrl-0 = <&i2c0_pins>;
  319. status = "okay";
  320. clock-frequency = <400000>;
  321. tps: tps@2d {
  322. reg = <0x2d>;
  323. };
  324. /* rtc0: rtc@51 {
  325. compatible = "nxp,pcf85063";
  326. reg = <0x51>;
  327. };*/
  328. };
  329. #if 1
  330. &i2c1 {
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&i2c1_pins>;
  333. status = "okay";
  334. clock-frequency = <400000>;
  335. rtc0: rtc@51 {
  336. compatible = "nxp,pcf85063";
  337. reg = <0x51>;
  338. };
  339. };
  340. #endif
  341. &usb {
  342. status = "okay";
  343. };
  344. &usb_ctrl_mod {
  345. status = "okay";
  346. };
  347. &usb0_phy {
  348. status = "okay";
  349. };
  350. &usb1_phy {
  351. status = "okay";
  352. };
  353. &usb0 {
  354. status = "okay";
  355. };
  356. &usb1 {
  357. status = "okay";
  358. dr_mode = "host";
  359. };
  360. &cppi41dma {
  361. status = "okay";
  362. };
  363. &elm {
  364. status = "okay";
  365. };
  366. #if 0
  367. &epwmss1 {
  368. status = "okay";
  369. ehrpwm1: pwm@48302200 {
  370. status = "okay";
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&ehrpwm1_pins>;
  373. };
  374. };
  375. &epwmss2 {
  376. status = "okay";
  377. ehrpwm2: pwm@48304200 {
  378. status = "okay";
  379. pinctrl-names = "default";
  380. pinctrl-0 = <&ehrpwm2_pins>;
  381. };
  382. };
  383. #endif
  384. &gpmc {
  385. status = "okay";
  386. pinctrl-names = "default", "sleep";
  387. pinctrl-0 = <&nandflash_pins_default>;
  388. pinctrl-1 = <&nandflash_pins_sleep>;
  389. /*ranges = <0 0 0x08000000 0x10000000>;*/ /* CS0: NAND */
  390. ranges = <0 0 0x08000000 0x80000000>; /*+++ vern,NAND,20181030 ---*/
  391. nand@0,0 {
  392. compatible = "ti,omap2-nand";
  393. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  394. interrupt-parent = <&gpmc>;
  395. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  396. <1 IRQ_TYPE_NONE>; /* termcount */
  397. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  398. ti,nand-ecc-opt = "bch8";
  399. ti,elm-id = <&elm>;
  400. nand-bus-width = <8>;
  401. gpmc,device-width = <1>;
  402. gpmc,sync-clk-ps = <0>;
  403. gpmc,cs-on-ns = <0>;
  404. gpmc,cs-rd-off-ns = <44>;
  405. gpmc,cs-wr-off-ns = <44>;
  406. gpmc,adv-on-ns = <6>;
  407. gpmc,adv-rd-off-ns = <34>;
  408. gpmc,adv-wr-off-ns = <44>;
  409. gpmc,we-on-ns = <0>;
  410. gpmc,we-off-ns = <40>;
  411. gpmc,oe-on-ns = <0>;
  412. gpmc,oe-off-ns = <54>;
  413. gpmc,access-ns = <64>;
  414. gpmc,rd-cycle-ns = <82>;
  415. gpmc,wr-cycle-ns = <82>;
  416. gpmc,wait-on-read = "true";
  417. gpmc,wait-on-write = "true";
  418. gpmc,bus-turnaround-ns = <0>;
  419. gpmc,cycle2cycle-delay-ns = <0>;
  420. gpmc,clk-activation-ns = <0>;
  421. gpmc,wait-monitoring-ns = <0>;
  422. gpmc,wr-access-ns = <40>;
  423. gpmc,wr-data-mux-bus-ns = <0>;
  424. /* MTD partition table */
  425. /* All SPL-* partitions are sized to minimal length
  426. * which can be independently programmable. For
  427. * NAND flash this is equal to size of erase-block */
  428. #address-cells = <1>;
  429. #size-cells = <1>;
  430. partition@0 {
  431. label = "SPL";
  432. reg = <0x00000000 0x00080000>;
  433. };
  434. partition@1 {
  435. label = "Primary u-boot";
  436. reg = <0x00080000 0x00100000>;
  437. };
  438. partition@2 {
  439. label = "u-boot-env";
  440. reg = <0x00180000 0x00080000>;
  441. };
  442. partition@3 {
  443. label = "Secondary u-boot";
  444. reg = <0x00200000 0x00100000>;
  445. };
  446. partition@4 {
  447. label = "Primary dtb";
  448. reg = <0x00300000 0x00080000>;
  449. };
  450. partition@5 {
  451. label = "Secondary dtb";
  452. reg = <0x00380000 0x00080000>;
  453. };
  454. partition@6 {
  455. label = "Primary kernel";
  456. reg = <0x00400000 0x00A00000>;
  457. };
  458. partition@7 {
  459. label = "Secondary kernel";
  460. reg = <0x00E00000 0x00A00000>;
  461. };
  462. partition@8 {
  463. label = "Primary rootfs";
  464. reg = <0x03000000 0x03000000>;
  465. };
  466. partition@9 {
  467. label = "Secondary rootfs";
  468. reg = <0x06000000 0x03000000>;
  469. };
  470. partition@10 {
  471. label = "Primary user configuration";
  472. reg = <0x09000000 0x00600000>;
  473. };
  474. partition@11 {
  475. label = "Secondary user configuration";
  476. reg = <0x09600000 0x00600000>;
  477. };
  478. partition@12 {
  479. label = "Factory default configuration";
  480. reg = <0x09C00000 0x00600000>;
  481. };
  482. partition@13 {
  483. label = "Storage";
  484. reg = <0x0A200000 0x75E00000>;
  485. };
  486. };
  487. };
  488. #include "tps65910.dtsi"
  489. &tps {
  490. vcc1-supply = <&vbat>;
  491. vcc2-supply = <&vbat>;
  492. vcc3-supply = <&vbat>;
  493. vcc4-supply = <&vbat>;
  494. vcc5-supply = <&vbat>;
  495. vcc6-supply = <&vbat>;
  496. vcc7-supply = <&vbat>;
  497. vccio-supply = <&vbat>;
  498. regulators {
  499. vrtc_reg: regulator@0 {
  500. regulator-always-on;
  501. };
  502. vio_reg: regulator@1 {
  503. regulator-always-on;
  504. };
  505. vdd1_reg: regulator@2 {
  506. /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
  507. regulator-name = "vdd_mpu";
  508. regulator-min-microvolt = <912500>;
  509. regulator-max-microvolt = <1378000>;
  510. regulator-boot-on;
  511. regulator-always-on;
  512. };
  513. vdd2_reg: regulator@3 {
  514. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  515. regulator-name = "vdd_core";
  516. regulator-min-microvolt = <912500>;
  517. regulator-max-microvolt = <1150000>;
  518. regulator-boot-on;
  519. regulator-always-on;
  520. };
  521. vdd3_reg: regulator@4 {
  522. regulator-always-on;
  523. };
  524. vdig1_reg: regulator@5 {
  525. regulator-always-on;
  526. };
  527. vdig2_reg: regulator@6 {
  528. regulator-always-on;
  529. };
  530. vpll_reg: regulator@7 {
  531. regulator-always-on;
  532. };
  533. vdac_reg: regulator@8 {
  534. regulator-always-on;
  535. };
  536. vaux1_reg: regulator@9 {
  537. regulator-always-on;
  538. };
  539. vaux2_reg: regulator@10 {
  540. regulator-always-on;
  541. };
  542. vaux33_reg: regulator@11 {
  543. regulator-always-on;
  544. };
  545. vmmc_reg: regulator@12 {
  546. regulator-min-microvolt = <1800000>;
  547. regulator-max-microvolt = <3300000>;
  548. regulator-always-on;
  549. };
  550. };
  551. };
  552. &mac {
  553. pinctrl-names = "default", "sleep";
  554. pinctrl-0 = <&cpsw_default>;
  555. pinctrl-1 = <&cpsw_sleep>;
  556. dual_emac = <1>;
  557. status = "okay";
  558. };
  559. &davinci_mdio {
  560. pinctrl-names = "default", "sleep";
  561. pinctrl-0 = <&davinci_mdio_default>;
  562. pinctrl-1 = <&davinci_mdio_sleep>;
  563. status = "okay";
  564. };
  565. &cpsw_emac0 {
  566. phy_id = <&davinci_mdio>, <1>;
  567. phy-mode = "mii";
  568. dual_emac_res_vlan = <1>;
  569. };
  570. &cpsw_emac1 {
  571. phy_id = <&davinci_mdio>, <2>;
  572. phy-mode = "mii";
  573. dual_emac_res_vlan = <2>;
  574. };
  575. &tscadc {
  576. status = "okay";
  577. /*tsc {
  578. ti,wires = <4>;
  579. ti,x-plate-resistance = <200>;
  580. ti,coordinate-readouts = <5>;
  581. ti,wire-config = <0x00 0x11 0x22 0x33>;
  582. };*/
  583. adc {
  584. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  585. };
  586. };
  587. &mmc1 {
  588. status = "okay";
  589. vmmc-supply = <&vmmc_reg>;
  590. bus-width = <4>;
  591. pinctrl-names = "default";
  592. pinctrl-0 = <&mmc1_pins_default>;
  593. cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
  594. };
  595. &edma {
  596. ti,edma-xbar-event-map = /bits/ 16 <1 12
  597. 2 13>;
  598. };
  599. &sham {
  600. status = "okay";
  601. };
  602. &aes {
  603. status = "okay";
  604. };
  605. &wkup_m3 {
  606. ti,scale-data-fw = "am335x-evm-scale-data.bin";
  607. };
  608. &dcan0 {
  609. status = "okay";
  610. pinctrl-names = "default";
  611. pinctrl-0 = <&dcan0_pins_default>;
  612. };
  613. &dcan1 {
  614. status = "okay";
  615. pinctrl-names = "default";
  616. pinctrl-0 = <&dcan1_pins_default>;
  617. };